In order to electrically couple the surface electrodes of a semiconductor chip to a circuit pattern on the surface of an insulating substrate via a lead frame, the surface electrodes of a semiconductor chip and the lead frame may be bonded together through a solder bonding layer having a thickness of 100 micrometers or more. Such a structure is used in some semiconductor devices known in the art (see Patent Document 1, for example). In this type of semiconductor device, distortion and thermal stress occurring in the solder bonding layer due to a difference in the linear expansion coefficient between the semiconductor chip and the lead frame may be reduced, which improves the reliability of bonding between the semiconductor chip and the lead frame.
Further, a buffer plate having a linear expansion coefficient whose value is between the linear expansion coefficient αc of a semiconductor device and the linear expansion coefficient αw of an interconnection member may be inserted between a surface electrode of the semiconductor device situated over an insulating substrate and one end of the interconnection member having the other end thereof bonded to an electrode on the insulating substrate. Such a structure is used in some semiconductor devices known in the art (see Patent Document 2, for example). This type of semiconductor device allows thermal stress applied to the bonding part to be reduced, thereby improving reliability against thermal cycle stress.